Error-Rate Prediction for Probabilistic Circuits with More General Structures

Abstract. A methodology has been proposed recently to predict errorrates of probabilistic circuits having a cascade structure. The objective of this poster is two fold. First, the methodology is applied, for the first time in the literature, to a probabilistic carry select adder, which has a more complex structure than the adders mentioned in previous papers. Second, it shows that the methodology is also applicable to some seemingly non-cascade circuits. The key technique is to appropriately group circuit components into various blocks before applying the methodology. Mark S. K. Lau, Keck Voon Ling, Arun Bhanu and Vincent J. Mooney III*